Computer systems typically include one or more processors or processing cores. These processors/cores are operatively coupled to other system components such as memory controllers, input/output hubs, and mass storage via some form of hardware connections, e.g., interconnects.
A communication protocol may be used to enable communication between these system components. Many such protocols provide for different layers to handle communication tasks. In some protocols, a physical layer is the layer that transmits messages along an interconnect and receives and processes messages from a corresponding physical layer of one or more other devices. Said physical layer may be coupled to a link layer that performs various functions such as error detection and correction. Said link layer may be coupled to a protocol layer which receives message packets from the link layer and further process them to route them to their appropriate destination locations.
An example protocol for use with a link as described above is the QuickPath Interconnect (QPI) protocol which is for point-to-point interconnects and provides for a multi-layer communication protocol for communication between various system devices such as processor cores, chipsets and so forth.
Each of the above described processors/cores may have an associated cache memory. Cache memory in computer systems may be kept coherent by managing transactions for memory addresses associated with particular locations in the system. Thus, a system's efficiency is directly related to how it manages the conflicts that arise amongst the different caches.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.